1. Field of the Invention
The present invention relates to an internal voltage generation control circuit and an internal voltage generation circuit using the same, and more particularly to a circuit for generating an internal voltage for an active operation of a semiconductor device and a circuit for controlling the generation of the internal voltage, wherein the internal voltage is supplied only in periods in which actual operations are performed after the active operation of the semiconductor device.
2. Description of the Related Art
Recently, the operating frequencies of semiconductor memory devices, such as a dynamic random access memory (DRAM), and the like etc., have become higher for high-speed operations of the memory devices, so the reduction in current consumption has been highlighted as an issue. In particular, the DRAM and the like, etc. have been widely applied to mobile terminals, etc. as well as being used as the main storage unit of computers. In this regard, the reduction in current consumption has become an essential requirement in designing semiconductor devices such as a DRAM, etc. However, a conventional circuit for generating an internal voltage for an active operation of a semiconductor device has the disadvantage of continuously generating and supplying an internal voltage not only in periods in which actual operations, such as an input operation, an output operation or, a row precharge operation, etc and., are performed after the active operation, but also in other periods in which the actual operations are not performed after the active operation, resulting in unnecessary current consumption, thus reducing power efficiency.
FIG. 1 is a block diagram showing the configuration of a conventional internal voltage generation circuit, FIG. 2 is a waveform diagram illustrating the operation of the conventional internal voltage generation circuit, and FIG. 3 is a circuit diagram of an internal voltage generator in the conventional internal voltage generation circuit. The above problem with the conventional internal voltage generation circuit will hereinafter be described in detail with reference to these drawings.
As shown in FIG. 1, the conventional internal voltage generation circuit comprises a signal generator 110 for receiving an external command signal CMD and a bank address signal BA and outputting a row active signal RACTP and a row precharge signal RPCGBP, an internal voltage generation control circuit 120 for receiving the row active signal RACTP and row precharge signal RPCGBP from the signal generator 110 and outputting an internal voltage generation control signal VINT_ACT, and an internal voltage generator 130 for generating an internal voltage VINT in response to the internal voltage generation control signal VINT_ACT.
A description will hereinafter be given of the operation of the conventional internal voltage generation circuit with the above-mentioned configuration. As shown in FIG. 2, when a bank address signal BA, a row address signal RA and an active command signal ACT are inputted synchronously with a rising edge of a clock CLK, a row active signal RACTP corresponding to a bank addressed by the bank address signal BA is outputted from the signal generator 110. Then, the internal voltage generation control circuit 120 outputs an internal voltage generation control signal VINT_ACT which makes a low to high level transition. This internal voltage generation control signal VINT_ACT is inputted to the internal voltage generator 130 shown in FIG. 3.
Accordingly, in FIG. 3, an NMOS transistor N6 is turned off and an NMOS transistor N3 is turned on, so that the internal voltage generator 130 is enabled. At this time, if a reference voltage REF_VINT is higher than a divided voltage Vx of the internal voltage VINT, an NMOS transistor N1 is turned on to pull a node A1 down to a low level, so as to turn a PMOS transistor P1 on. As the PMOS transistor P1 is turned on, the potential of a node B1 rises to a high level, thereby causing an NMOS transistor N5 to be turned on, thus pulling a node C1 down to a low level. As a result, a PMOS transistor P8 is turned on to supply an external voltage VDD to an output node D1, so that the internal voltage VINT rises.
On the other hand, if the reference voltage REF_VINT is lower than the divided voltage Vx of the internal voltage VINT, an NMOS transistor N2 is turned on to pull a node E1 down to a low level, so as to turn a PMOS transistor P6 on. As the PMOS transistor P6 is turned on, the potential of the node C1 rises to a high level, thereby causing the PMOS transistor P8 to be turned off. As a result, the external voltage VDD is not supplied to the output node D1, so that the internal voltage VINT falls or is maintained as it is.
Thereafter, as shown in FIG. 2, if a bank address signal BA and a precharge command signal PCG are enabled, then a row precharge signal RPCGBP is outputted from the signal generator 110. Then, the internal voltage generation control signal VINT_ACT from the internal voltage generation control circuit 120 is disabled from high to low in level after a delay time Td. Hence, the NMOS transistor N6 in FIG. 3 is turned on, thereby causing the internal voltage generator 130 to be disabled.
As stated above, the conventional internal voltage generation circuit and internal voltage generation control circuit are adapted to, until the precharge command PCG is inputted after the active operation, continuously enablinge the internal voltage generator 130 to supply the internal voltage VINT. As a result, the conventional internal voltage generation circuit continuously generates and supplies the internal voltage not only in periods in which actual operations, such as an input operation, an output operation, a row precharge operation, and the like etc., are performed after the active operation, but also in other periods in which the actual operations are not performed after the active operation, resulting in unnecessary consumption of a large amount of current, thus reducing power efficiency.